//4-bit counter
module f_counter (count, clk, rst);
input clk, rst;
output [3:0]count;
reg [3:0]count;
always @ (posedge clk or negedge rst)
if(!rst) count =0;
else
count = count + 1;
endmodule
//test 4-bit counter
module f_counter_test;
reg clk, rst;
wire [3:0]count;
f_counter f_cnt (count, clk, rst);
initial
begin
clk = 0;
rst = 0;
#10 rst = 1;
forever #25 clk = !clk;
end
endmodule
